We get stuff working and then we break it again.
The morning is tough. The logic is fine, the programming file for the FPGA (field programmable gate array) compiles and configures, and the software runs on the board. However, when I stick a probe on the pins of interest (those through which the control signals are passed to the chips), the oscilloscope flatlines. The system is obviously getting hung up somewhere and I am instructed to find out where. This involves putting the code through a simulator, which involves re-learning how to use the simulator, which…You get the picture. And the simulator, after appropriate sacrifices to the ModelSim gods, reveals that the logic is fine, the programming file is fine, etc. Back to the hardware. I am told to bring the counter value, which is incremented to step the system sequentially through the different states, out to the LEDs so we can see for sure where it's getting hung up. Easy enough. I do so and suddenly the system works perfectly. No more flatlines, the scope shows all the signals pulsing exactly as they should down to the nanosecond. The FIFO fills up and is emptied out by the PC. Beautiful.
The only change I made was to direct a different signal out to the LEDs. Is this what they call the observer effect? The lazy-ass system shapes right up when I look at it closely.
The hardware synthesis tools are a fickle lot indeed.
But, hey, it's working. Time to add the next level of functionality. I wire some of the control signals to a dip switch and send one into a data pin of the FIFO.
It stops working. More specifically, it works wonderfully, except that the FIFO stays empty no matter how many times it is written.
The hardware synthesis tools are a fickle lot indeed.
309 words | May 28, 2004 08:56 PM | Rocket science